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<a href="#define-members">Macros</a> &#124;
<a href="#func-members">Functions</a>  </div>
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<div class="title">xiic_l.h File Reference</div>  </div>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:gab81f7edf097fc4a885fd6134a288a817"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#gab81f7edf097fc4a885fd6134a288a817">XIIC_READ_OPERATION</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:gab81f7edf097fc4a885fd6134a288a817"><td class="mdescLeft">&#160;</td><td class="mdescRight">The following constants are used to specify whether to do Read or a Write operation on IIC bus.  <a href="group__iic__v3__1.html#gab81f7edf097fc4a885fd6134a288a817">More...</a><br /></td></tr>
<tr class="separator:gab81f7edf097fc4a885fd6134a288a817"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8bb1f3ab452d41daf06eff8d61048fe8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga8bb1f3ab452d41daf06eff8d61048fe8">XIIC_WRITE_OPERATION</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga8bb1f3ab452d41daf06eff8d61048fe8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write operation on the IIC bus.  <a href="group__iic__v3__1.html#ga8bb1f3ab452d41daf06eff8d61048fe8">More...</a><br /></td></tr>
<tr class="separator:ga8bb1f3ab452d41daf06eff8d61048fe8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa0040c82cb3f8c0bbff61cbbad86e1ac"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#gaa0040c82cb3f8c0bbff61cbbad86e1ac">XIIC_MASTER_ROLE</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:gaa0040c82cb3f8c0bbff61cbbad86e1ac"><td class="mdescLeft">&#160;</td><td class="mdescRight">The following constants are used with the transmit FIFO fill function to specify the role which the IIC device is acting as, a master or a slave.  <a href="group__iic__v3__1.html#gaa0040c82cb3f8c0bbff61cbbad86e1ac">More...</a><br /></td></tr>
<tr class="separator:gaa0040c82cb3f8c0bbff61cbbad86e1ac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga85bbbc139ce96e43b2f1f947d0652539"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga85bbbc139ce96e43b2f1f947d0652539">XIIC_SLAVE_ROLE</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga85bbbc139ce96e43b2f1f947d0652539"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave on the IIC bus.  <a href="group__iic__v3__1.html#ga85bbbc139ce96e43b2f1f947d0652539">More...</a><br /></td></tr>
<tr class="separator:ga85bbbc139ce96e43b2f1f947d0652539"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacdf6b790e752c7f789c81ee4721bafe8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#gacdf6b790e752c7f789c81ee4721bafe8">XIIC_STOP</a>&#160;&#160;&#160;0x00</td></tr>
<tr class="memdesc:gacdf6b790e752c7f789c81ee4721bafe8"><td class="mdescLeft">&#160;</td><td class="mdescRight">The following constants are used with Transmit Function (XIic_Send) to specify whether to STOP after the current transfer of data or own the bus with a Repeated start.  <a href="group__iic__v3__1.html#gacdf6b790e752c7f789c81ee4721bafe8">More...</a><br /></td></tr>
<tr class="separator:gacdf6b790e752c7f789c81ee4721bafe8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae2c7104aa187b965ff0adbe3d4e1bccb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#gae2c7104aa187b965ff0adbe3d4e1bccb">XIIC_REPEATED_START</a>&#160;&#160;&#160;0x01</td></tr>
<tr class="memdesc:gae2c7104aa187b965ff0adbe3d4e1bccb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Donot Send a stop on the IIC bus after the current data transfer.  <a href="group__iic__v3__1.html#gae2c7104aa187b965ff0adbe3d4e1bccb">More...</a><br /></td></tr>
<tr class="separator:gae2c7104aa187b965ff0adbe3d4e1bccb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab28be58b11c65ecc54fc2f0c300412c1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#gab28be58b11c65ecc54fc2f0c300412c1">XIic_ReadReg</a>(BaseAddress,  RegOffset)&#160;&#160;&#160;XIic_In32((BaseAddress) + (RegOffset))</td></tr>
<tr class="memdesc:gab28be58b11c65ecc54fc2f0c300412c1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read from the specified IIC device register.  <a href="group__iic__v3__1.html#gab28be58b11c65ecc54fc2f0c300412c1">More...</a><br /></td></tr>
<tr class="separator:gab28be58b11c65ecc54fc2f0c300412c1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7a9318f43afc81c1dbd30a27587ba51d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga7a9318f43afc81c1dbd30a27587ba51d">XIic_WriteReg</a>(BaseAddress,  RegOffset,  RegisterValue)&#160;&#160;&#160;XIic_Out32((BaseAddress) + (RegOffset), (RegisterValue))</td></tr>
<tr class="memdesc:ga7a9318f43afc81c1dbd30a27587ba51d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write to the specified IIC device register.  <a href="group__iic__v3__1.html#ga7a9318f43afc81c1dbd30a27587ba51d">More...</a><br /></td></tr>
<tr class="separator:ga7a9318f43afc81c1dbd30a27587ba51d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga17d0df7020d5264d20bbc36d276e276e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga17d0df7020d5264d20bbc36d276e276e">XIic_IntrGlobalDisable</a>(BaseAddress)&#160;&#160;&#160;<a class="el" href="group__iic__v3__1.html#ga7a9318f43afc81c1dbd30a27587ba51d">XIic_WriteReg</a>((BaseAddress), <a class="el" href="group__iic__v3__1.html#gaa27d0e422717f97fac36688f403d320a">XIIC_DGIER_OFFSET</a>, 0)</td></tr>
<tr class="memdesc:ga17d0df7020d5264d20bbc36d276e276e"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro disables all interrupts for the device by writing to the Global interrupt enable register.  <a href="group__iic__v3__1.html#ga17d0df7020d5264d20bbc36d276e276e">More...</a><br /></td></tr>
<tr class="separator:ga17d0df7020d5264d20bbc36d276e276e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7071fcf4cf60d65fd862653fa34faa21"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga7071fcf4cf60d65fd862653fa34faa21">XIic_IntrGlobalEnable</a>(BaseAddress)</td></tr>
<tr class="memdesc:ga7071fcf4cf60d65fd862653fa34faa21"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro writes to the global interrupt enable register to enable interrupts from the device.  <a href="group__iic__v3__1.html#ga7071fcf4cf60d65fd862653fa34faa21">More...</a><br /></td></tr>
<tr class="separator:ga7071fcf4cf60d65fd862653fa34faa21"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa839067df3b55f3181db24ebd8db3187"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#gaa839067df3b55f3181db24ebd8db3187">XIic_IsIntrGlobalEnabled</a>(BaseAddress)</td></tr>
<tr class="memdesc:gaa839067df3b55f3181db24ebd8db3187"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function determines if interrupts are enabled at the global level by reading the global interrupt register.  <a href="group__iic__v3__1.html#gaa839067df3b55f3181db24ebd8db3187">More...</a><br /></td></tr>
<tr class="separator:gaa839067df3b55f3181db24ebd8db3187"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3bc448908013aceb690c84fdbb7d66a8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga3bc448908013aceb690c84fdbb7d66a8">XIic_WriteIisr</a>(BaseAddress,  Status)&#160;&#160;&#160;<a class="el" href="group__iic__v3__1.html#ga7a9318f43afc81c1dbd30a27587ba51d">XIic_WriteReg</a>((BaseAddress), <a class="el" href="group__iic__v3__1.html#gafe67d115440977750c9a7299eb499798">XIIC_IISR_OFFSET</a>, (Status))</td></tr>
<tr class="memdesc:ga3bc448908013aceb690c84fdbb7d66a8"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the Interrupt status register to the specified value.  <a href="group__iic__v3__1.html#ga3bc448908013aceb690c84fdbb7d66a8">More...</a><br /></td></tr>
<tr class="separator:ga3bc448908013aceb690c84fdbb7d66a8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf69a6487ad62b105aa3bb8d0e25b7fe7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#gaf69a6487ad62b105aa3bb8d0e25b7fe7">XIic_ReadIisr</a>(BaseAddress)&#160;&#160;&#160;<a class="el" href="group__iic__v3__1.html#gab28be58b11c65ecc54fc2f0c300412c1">XIic_ReadReg</a>((BaseAddress), <a class="el" href="group__iic__v3__1.html#gafe67d115440977750c9a7299eb499798">XIIC_IISR_OFFSET</a>)</td></tr>
<tr class="memdesc:gaf69a6487ad62b105aa3bb8d0e25b7fe7"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function gets the contents of the Interrupt Status Register.  <a href="group__iic__v3__1.html#gaf69a6487ad62b105aa3bb8d0e25b7fe7">More...</a><br /></td></tr>
<tr class="separator:gaf69a6487ad62b105aa3bb8d0e25b7fe7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2f926a076e9a6b80bea46664d2e55ee9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga2f926a076e9a6b80bea46664d2e55ee9">XIic_WriteIier</a>(BaseAddress,  Enable)&#160;&#160;&#160;<a class="el" href="group__iic__v3__1.html#ga7a9318f43afc81c1dbd30a27587ba51d">XIic_WriteReg</a>((BaseAddress), <a class="el" href="group__iic__v3__1.html#ga6a6353babc7347287755655c810a1758">XIIC_IIER_OFFSET</a>, (Enable))</td></tr>
<tr class="memdesc:ga2f926a076e9a6b80bea46664d2e55ee9"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the contents of the Interrupt Enable Register.  <a href="group__iic__v3__1.html#ga2f926a076e9a6b80bea46664d2e55ee9">More...</a><br /></td></tr>
<tr class="separator:ga2f926a076e9a6b80bea46664d2e55ee9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaee17ffc86a8270abeb1319e8c67ccce5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#gaee17ffc86a8270abeb1319e8c67ccce5">XIic_ReadIier</a>(BaseAddress)&#160;&#160;&#160;<a class="el" href="group__iic__v3__1.html#gab28be58b11c65ecc54fc2f0c300412c1">XIic_ReadReg</a>((BaseAddress), <a class="el" href="group__iic__v3__1.html#ga6a6353babc7347287755655c810a1758">XIIC_IIER_OFFSET</a>)</td></tr>
<tr class="memdesc:gaee17ffc86a8270abeb1319e8c67ccce5"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function gets the Interrupt Enable Register contents.  <a href="group__iic__v3__1.html#gaee17ffc86a8270abeb1319e8c67ccce5">More...</a><br /></td></tr>
<tr class="separator:gaee17ffc86a8270abeb1319e8c67ccce5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf8fa6ffa77af5942fa1dbd1b5a666d55"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#gaf8fa6ffa77af5942fa1dbd1b5a666d55">XIic_ClearIisr</a>(BaseAddress,  InterruptMask)</td></tr>
<tr class="memdesc:gaf8fa6ffa77af5942fa1dbd1b5a666d55"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro clears the specified interrupt in the Interrupt status register.  <a href="group__iic__v3__1.html#gaf8fa6ffa77af5942fa1dbd1b5a666d55">More...</a><br /></td></tr>
<tr class="separator:gaf8fa6ffa77af5942fa1dbd1b5a666d55"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga89d095e79795958bcbc15238a7bbfa32"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga89d095e79795958bcbc15238a7bbfa32">XIic_Send7BitAddress</a>(BaseAddress,  SlaveAddress,  Operation)</td></tr>
<tr class="memdesc:ga89d095e79795958bcbc15238a7bbfa32"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro sends the address for a 7 bit address during both read and write operations.  <a href="group__iic__v3__1.html#ga89d095e79795958bcbc15238a7bbfa32">More...</a><br /></td></tr>
<tr class="separator:ga89d095e79795958bcbc15238a7bbfa32"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga81d32f9fd29736e9f9c7ef345527386b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga81d32f9fd29736e9f9c7ef345527386b">XIic_DynSend7BitAddress</a>(BaseAddress,  SlaveAddress,  Operation)</td></tr>
<tr class="memdesc:ga81d32f9fd29736e9f9c7ef345527386b"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro sends the address for a 7 bit address during both read and write operations.  <a href="group__iic__v3__1.html#ga81d32f9fd29736e9f9c7ef345527386b">More...</a><br /></td></tr>
<tr class="separator:ga81d32f9fd29736e9f9c7ef345527386b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga682d21ed5020daa5b5a863bbffb35cc5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga682d21ed5020daa5b5a863bbffb35cc5">XIic_DynSendStartStopAddress</a>(BaseAddress,  SlaveAddress,  Operation)</td></tr>
<tr class="memdesc:ga682d21ed5020daa5b5a863bbffb35cc5"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro sends the address, start and stop for a 7 bit address during both write operations.  <a href="group__iic__v3__1.html#ga682d21ed5020daa5b5a863bbffb35cc5">More...</a><br /></td></tr>
<tr class="separator:ga682d21ed5020daa5b5a863bbffb35cc5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga22446f72b705b950e4b485ab9cdd2ae6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga22446f72b705b950e4b485ab9cdd2ae6">XIic_DynSendStop</a>(BaseAddress,  ByteCount)</td></tr>
<tr class="memdesc:ga22446f72b705b950e4b485ab9cdd2ae6"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro sends a stop condition on IIC bus for Dynamic logic.  <a href="group__iic__v3__1.html#ga22446f72b705b950e4b485ab9cdd2ae6">More...</a><br /></td></tr>
<tr class="separator:ga22446f72b705b950e4b485ab9cdd2ae6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Register Map</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Register offsets for the <a class="el" href="struct_x_iic.html" title="The XIic driver instance data. ">XIic</a> device. </p>
</div></td></tr>
<tr class="memitem:gaa27d0e422717f97fac36688f403d320a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#gaa27d0e422717f97fac36688f403d320a">XIIC_DGIER_OFFSET</a>&#160;&#160;&#160;0x1C</td></tr>
<tr class="memdesc:gaa27d0e422717f97fac36688f403d320a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Global Interrupt Enable Register.  <a href="group__iic__v3__1.html#gaa27d0e422717f97fac36688f403d320a">More...</a><br /></td></tr>
<tr class="separator:gaa27d0e422717f97fac36688f403d320a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafe67d115440977750c9a7299eb499798"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#gafe67d115440977750c9a7299eb499798">XIIC_IISR_OFFSET</a>&#160;&#160;&#160;0x20</td></tr>
<tr class="memdesc:gafe67d115440977750c9a7299eb499798"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Status Register.  <a href="group__iic__v3__1.html#gafe67d115440977750c9a7299eb499798">More...</a><br /></td></tr>
<tr class="separator:gafe67d115440977750c9a7299eb499798"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6a6353babc7347287755655c810a1758"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga6a6353babc7347287755655c810a1758">XIIC_IIER_OFFSET</a>&#160;&#160;&#160;0x28</td></tr>
<tr class="memdesc:ga6a6353babc7347287755655c810a1758"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Enable Register.  <a href="group__iic__v3__1.html#ga6a6353babc7347287755655c810a1758">More...</a><br /></td></tr>
<tr class="separator:ga6a6353babc7347287755655c810a1758"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2129f15b6d659403e4aa18355aa67884"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga2129f15b6d659403e4aa18355aa67884">XIIC_RESETR_OFFSET</a>&#160;&#160;&#160;0x40</td></tr>
<tr class="memdesc:ga2129f15b6d659403e4aa18355aa67884"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reset Register.  <a href="group__iic__v3__1.html#ga2129f15b6d659403e4aa18355aa67884">More...</a><br /></td></tr>
<tr class="separator:ga2129f15b6d659403e4aa18355aa67884"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga03585e458e3c5adf56986e7c2c3d9d42"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga03585e458e3c5adf56986e7c2c3d9d42">XIIC_CR_REG_OFFSET</a>&#160;&#160;&#160;0x100</td></tr>
<tr class="memdesc:ga03585e458e3c5adf56986e7c2c3d9d42"><td class="mdescLeft">&#160;</td><td class="mdescRight">Control Register.  <a href="group__iic__v3__1.html#ga03585e458e3c5adf56986e7c2c3d9d42">More...</a><br /></td></tr>
<tr class="separator:ga03585e458e3c5adf56986e7c2c3d9d42"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa039f3dea3b57add15de333f733b5561"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#gaa039f3dea3b57add15de333f733b5561">XIIC_SR_REG_OFFSET</a>&#160;&#160;&#160;0x104</td></tr>
<tr class="memdesc:gaa039f3dea3b57add15de333f733b5561"><td class="mdescLeft">&#160;</td><td class="mdescRight">Status Register.  <a href="group__iic__v3__1.html#gaa039f3dea3b57add15de333f733b5561">More...</a><br /></td></tr>
<tr class="separator:gaa039f3dea3b57add15de333f733b5561"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga63ef537f0fba0aa0c68f9be05516c6c9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga63ef537f0fba0aa0c68f9be05516c6c9">XIIC_DTR_REG_OFFSET</a>&#160;&#160;&#160;0x108</td></tr>
<tr class="memdesc:ga63ef537f0fba0aa0c68f9be05516c6c9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Tx Register.  <a href="group__iic__v3__1.html#ga63ef537f0fba0aa0c68f9be05516c6c9">More...</a><br /></td></tr>
<tr class="separator:ga63ef537f0fba0aa0c68f9be05516c6c9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8b1aea0734d4d8fc3d883ef2d6d63494"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga8b1aea0734d4d8fc3d883ef2d6d63494">XIIC_DRR_REG_OFFSET</a>&#160;&#160;&#160;0x10C</td></tr>
<tr class="memdesc:ga8b1aea0734d4d8fc3d883ef2d6d63494"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Rx Register.  <a href="group__iic__v3__1.html#ga8b1aea0734d4d8fc3d883ef2d6d63494">More...</a><br /></td></tr>
<tr class="separator:ga8b1aea0734d4d8fc3d883ef2d6d63494"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga831a9fbdcfebad501e336231321be40a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga831a9fbdcfebad501e336231321be40a">XIIC_ADR_REG_OFFSET</a>&#160;&#160;&#160;0x110</td></tr>
<tr class="memdesc:ga831a9fbdcfebad501e336231321be40a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Address Register.  <a href="group__iic__v3__1.html#ga831a9fbdcfebad501e336231321be40a">More...</a><br /></td></tr>
<tr class="separator:ga831a9fbdcfebad501e336231321be40a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3b1a6b1edb70a36a0d44ccf0d39a885f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga3b1a6b1edb70a36a0d44ccf0d39a885f">XIIC_TFO_REG_OFFSET</a>&#160;&#160;&#160;0x114</td></tr>
<tr class="memdesc:ga3b1a6b1edb70a36a0d44ccf0d39a885f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tx FIFO Occupancy.  <a href="group__iic__v3__1.html#ga3b1a6b1edb70a36a0d44ccf0d39a885f">More...</a><br /></td></tr>
<tr class="separator:ga3b1a6b1edb70a36a0d44ccf0d39a885f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabe647af8022928553f2fd3bb05bfa80a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#gabe647af8022928553f2fd3bb05bfa80a">XIIC_RFO_REG_OFFSET</a>&#160;&#160;&#160;0x118</td></tr>
<tr class="memdesc:gabe647af8022928553f2fd3bb05bfa80a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Rx FIFO Occupancy.  <a href="group__iic__v3__1.html#gabe647af8022928553f2fd3bb05bfa80a">More...</a><br /></td></tr>
<tr class="separator:gabe647af8022928553f2fd3bb05bfa80a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf50b1672278bdf573cd74e36768b0cda"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#gaf50b1672278bdf573cd74e36768b0cda">XIIC_TBA_REG_OFFSET</a>&#160;&#160;&#160;0x11C</td></tr>
<tr class="memdesc:gaf50b1672278bdf573cd74e36768b0cda"><td class="mdescLeft">&#160;</td><td class="mdescRight">10 Bit Address reg  <a href="group__iic__v3__1.html#gaf50b1672278bdf573cd74e36768b0cda">More...</a><br /></td></tr>
<tr class="separator:gaf50b1672278bdf573cd74e36768b0cda"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad032470e4ff2a3760aa63f2c3d7e5240"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#gad032470e4ff2a3760aa63f2c3d7e5240">XIIC_RFD_REG_OFFSET</a>&#160;&#160;&#160;0x120</td></tr>
<tr class="memdesc:gad032470e4ff2a3760aa63f2c3d7e5240"><td class="mdescLeft">&#160;</td><td class="mdescRight">Rx FIFO Depth reg.  <a href="group__iic__v3__1.html#gad032470e4ff2a3760aa63f2c3d7e5240">More...</a><br /></td></tr>
<tr class="separator:gad032470e4ff2a3760aa63f2c3d7e5240"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf901951024f3144cd51ce84d897a5f5b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#gaf901951024f3144cd51ce84d897a5f5b">XIIC_GPO_REG_OFFSET</a>&#160;&#160;&#160;0x124</td></tr>
<tr class="memdesc:gaf901951024f3144cd51ce84d897a5f5b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Output Register.  <a href="group__iic__v3__1.html#gaf901951024f3144cd51ce84d897a5f5b">More...</a><br /></td></tr>
<tr class="separator:gaf901951024f3144cd51ce84d897a5f5b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Device Global Interrupt Enable Register masks (CR) mask(s)</div></td></tr>
<tr class="memitem:gaec62fb2c2f3894266187fa408c256891"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#gaec62fb2c2f3894266187fa408c256891">XIIC_GINTR_ENABLE_MASK</a>&#160;&#160;&#160;0x80000000</td></tr>
<tr class="memdesc:gaec62fb2c2f3894266187fa408c256891"><td class="mdescLeft">&#160;</td><td class="mdescRight">Global Interrupt Enable Mask.  <a href="group__iic__v3__1.html#gaec62fb2c2f3894266187fa408c256891">More...</a><br /></td></tr>
<tr class="separator:gaec62fb2c2f3894266187fa408c256891"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">IIC Device Interrupt Status/Enable (INTR) Register Masks</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p><b> Interrupt Status Register (IISR) </b></p>
<p>This register holds the interrupt status flags for the Spi device.</p>
<p><b> Interrupt Enable Register (IIER) </b></p>
<p>This register is used to enable interrupt sources for the IIC device. Writing a '1' to a bit in this register enables the corresponding Interrupt. Writing a '0' to a bit in this register disables the corresponding Interrupt.</p>
<p>IISR/IIER registers have the same bit definitions and are only defined once. </p>
</div></td></tr>
<tr class="memitem:gabb6a638c0aa6ee9e3b50dc5d2ca56770"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#gabb6a638c0aa6ee9e3b50dc5d2ca56770">XIIC_INTR_ARB_LOST_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:gabb6a638c0aa6ee9e3b50dc5d2ca56770"><td class="mdescLeft">&#160;</td><td class="mdescRight">1 = Arbitration lost  <a href="group__iic__v3__1.html#gabb6a638c0aa6ee9e3b50dc5d2ca56770">More...</a><br /></td></tr>
<tr class="separator:gabb6a638c0aa6ee9e3b50dc5d2ca56770"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa1ea99d449fd02f69d41d0f41f093282"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#gaa1ea99d449fd02f69d41d0f41f093282">XIIC_INTR_TX_ERROR_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:gaa1ea99d449fd02f69d41d0f41f093282"><td class="mdescLeft">&#160;</td><td class="mdescRight">1 = Tx error/msg complete  <a href="group__iic__v3__1.html#gaa1ea99d449fd02f69d41d0f41f093282">More...</a><br /></td></tr>
<tr class="separator:gaa1ea99d449fd02f69d41d0f41f093282"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadc15e89e891805d58f729c4d1f56b093"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#gadc15e89e891805d58f729c4d1f56b093">XIIC_INTR_TX_EMPTY_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:gadc15e89e891805d58f729c4d1f56b093"><td class="mdescLeft">&#160;</td><td class="mdescRight">1 = Tx FIFO/reg empty  <a href="group__iic__v3__1.html#gadc15e89e891805d58f729c4d1f56b093">More...</a><br /></td></tr>
<tr class="separator:gadc15e89e891805d58f729c4d1f56b093"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac96fa03c6a514cd87cb9deadaef7e574"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#gac96fa03c6a514cd87cb9deadaef7e574">XIIC_INTR_RX_FULL_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:gac96fa03c6a514cd87cb9deadaef7e574"><td class="mdescLeft">&#160;</td><td class="mdescRight">1 = Rx FIFO/reg=OCY level  <a href="group__iic__v3__1.html#gac96fa03c6a514cd87cb9deadaef7e574">More...</a><br /></td></tr>
<tr class="separator:gac96fa03c6a514cd87cb9deadaef7e574"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga52e6f9aadc4cc828509347c6768d2c25"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga52e6f9aadc4cc828509347c6768d2c25">XIIC_INTR_BNB_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:ga52e6f9aadc4cc828509347c6768d2c25"><td class="mdescLeft">&#160;</td><td class="mdescRight">1 = Bus not busy  <a href="group__iic__v3__1.html#ga52e6f9aadc4cc828509347c6768d2c25">More...</a><br /></td></tr>
<tr class="separator:ga52e6f9aadc4cc828509347c6768d2c25"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga88cf05913ad5693c477993c2af6cbd7e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga88cf05913ad5693c477993c2af6cbd7e">XIIC_INTR_AAS_MASK</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:ga88cf05913ad5693c477993c2af6cbd7e"><td class="mdescLeft">&#160;</td><td class="mdescRight">1 = When addr as slave  <a href="group__iic__v3__1.html#ga88cf05913ad5693c477993c2af6cbd7e">More...</a><br /></td></tr>
<tr class="separator:ga88cf05913ad5693c477993c2af6cbd7e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab153bb7f21133bf7471c70f4089494a5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#gab153bb7f21133bf7471c70f4089494a5">XIIC_INTR_NAAS_MASK</a>&#160;&#160;&#160;0x00000040</td></tr>
<tr class="memdesc:gab153bb7f21133bf7471c70f4089494a5"><td class="mdescLeft">&#160;</td><td class="mdescRight">1 = Not addr as slave  <a href="group__iic__v3__1.html#gab153bb7f21133bf7471c70f4089494a5">More...</a><br /></td></tr>
<tr class="separator:gab153bb7f21133bf7471c70f4089494a5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4af241dbcd0cb4184fe594d09954f69c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga4af241dbcd0cb4184fe594d09954f69c">XIIC_INTR_TX_HALF_MASK</a>&#160;&#160;&#160;0x00000080</td></tr>
<tr class="memdesc:ga4af241dbcd0cb4184fe594d09954f69c"><td class="mdescLeft">&#160;</td><td class="mdescRight">1 = Tx FIFO half empty  <a href="group__iic__v3__1.html#ga4af241dbcd0cb4184fe594d09954f69c">More...</a><br /></td></tr>
<tr class="separator:ga4af241dbcd0cb4184fe594d09954f69c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac9441942c102ac8a8485609d98ba5d5c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#gac9441942c102ac8a8485609d98ba5d5c">XIIC_TX_INTERRUPTS</a></td></tr>
<tr class="memdesc:gac9441942c102ac8a8485609d98ba5d5c"><td class="mdescLeft">&#160;</td><td class="mdescRight">All Tx interrupts commonly used.  <a href="group__iic__v3__1.html#gac9441942c102ac8a8485609d98ba5d5c">More...</a><br /></td></tr>
<tr class="separator:gac9441942c102ac8a8485609d98ba5d5c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac942198f619f45e2705457967e1683c8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#gac942198f619f45e2705457967e1683c8">XIIC_TX_RX_INTERRUPTS</a>&#160;&#160;&#160;(<a class="el" href="group__iic__v3__1.html#gac96fa03c6a514cd87cb9deadaef7e574">XIIC_INTR_RX_FULL_MASK</a> | <a class="el" href="group__iic__v3__1.html#gac9441942c102ac8a8485609d98ba5d5c">XIIC_TX_INTERRUPTS</a>)</td></tr>
<tr class="memdesc:gac942198f619f45e2705457967e1683c8"><td class="mdescLeft">&#160;</td><td class="mdescRight">All interrupts commonly used.  <a href="group__iic__v3__1.html#gac942198f619f45e2705457967e1683c8">More...</a><br /></td></tr>
<tr class="separator:gac942198f619f45e2705457967e1683c8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Reset Register mask</div></td></tr>
<tr class="memitem:gad29589acad66518bac5f21a670ccc9a5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#gad29589acad66518bac5f21a670ccc9a5">XIIC_RESET_MASK</a>&#160;&#160;&#160;0x0000000A</td></tr>
<tr class="memdesc:gad29589acad66518bac5f21a670ccc9a5"><td class="mdescLeft">&#160;</td><td class="mdescRight">RESET Mask.  <a href="group__iic__v3__1.html#gad29589acad66518bac5f21a670ccc9a5">More...</a><br /></td></tr>
<tr class="separator:gad29589acad66518bac5f21a670ccc9a5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Control Register masks (CR) mask(s)</div></td></tr>
<tr class="memitem:gaa4fa9698cb076131f2d4571ef3bae6f3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#gaa4fa9698cb076131f2d4571ef3bae6f3">XIIC_CR_ENABLE_DEVICE_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:gaa4fa9698cb076131f2d4571ef3bae6f3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Device enable = 1.  <a href="group__iic__v3__1.html#gaa4fa9698cb076131f2d4571ef3bae6f3">More...</a><br /></td></tr>
<tr class="separator:gaa4fa9698cb076131f2d4571ef3bae6f3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2342662b2911c5aea24b397e17be7e41"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga2342662b2911c5aea24b397e17be7e41">XIIC_CR_TX_FIFO_RESET_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:ga2342662b2911c5aea24b397e17be7e41"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transmit FIFO reset=1.  <a href="group__iic__v3__1.html#ga2342662b2911c5aea24b397e17be7e41">More...</a><br /></td></tr>
<tr class="separator:ga2342662b2911c5aea24b397e17be7e41"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafa18a79f31c286ce3daf88d677096d9d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#gafa18a79f31c286ce3daf88d677096d9d">XIIC_CR_MSMS_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:gafa18a79f31c286ce3daf88d677096d9d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Master starts Txing=1.  <a href="group__iic__v3__1.html#gafa18a79f31c286ce3daf88d677096d9d">More...</a><br /></td></tr>
<tr class="separator:gafa18a79f31c286ce3daf88d677096d9d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaefca9cb59ce820ea4fbb4c35f5a1fa55"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#gaefca9cb59ce820ea4fbb4c35f5a1fa55">XIIC_CR_DIR_IS_TX_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:gaefca9cb59ce820ea4fbb4c35f5a1fa55"><td class="mdescLeft">&#160;</td><td class="mdescRight">Dir of Tx.  <a href="group__iic__v3__1.html#gaefca9cb59ce820ea4fbb4c35f5a1fa55">More...</a><br /></td></tr>
<tr class="separator:gaefca9cb59ce820ea4fbb4c35f5a1fa55"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga79990adaa6f077302644d7b787b19c53"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga79990adaa6f077302644d7b787b19c53">XIIC_CR_NO_ACK_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:ga79990adaa6f077302644d7b787b19c53"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tx Ack.  <a href="group__iic__v3__1.html#ga79990adaa6f077302644d7b787b19c53">More...</a><br /></td></tr>
<tr class="separator:ga79990adaa6f077302644d7b787b19c53"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5d0c5d60de4fd0ca22e12b8be3870656"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga5d0c5d60de4fd0ca22e12b8be3870656">XIIC_CR_REPEATED_START_MASK</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:ga5d0c5d60de4fd0ca22e12b8be3870656"><td class="mdescLeft">&#160;</td><td class="mdescRight">Repeated start = 1.  <a href="group__iic__v3__1.html#ga5d0c5d60de4fd0ca22e12b8be3870656">More...</a><br /></td></tr>
<tr class="separator:ga5d0c5d60de4fd0ca22e12b8be3870656"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac9dda6b07f8f4d2962b8833b05b8603b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#gac9dda6b07f8f4d2962b8833b05b8603b">XIIC_CR_GENERAL_CALL_MASK</a>&#160;&#160;&#160;0x00000040</td></tr>
<tr class="memdesc:gac9dda6b07f8f4d2962b8833b05b8603b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Gen Call enabled = 1.  <a href="group__iic__v3__1.html#gac9dda6b07f8f4d2962b8833b05b8603b">More...</a><br /></td></tr>
<tr class="separator:gac9dda6b07f8f4d2962b8833b05b8603b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Status Register masks (SR) mask(s)</div></td></tr>
<tr class="memitem:gaac5399a034245e8adaa09f301bc4968c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#gaac5399a034245e8adaa09f301bc4968c">XIIC_SR_GEN_CALL_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:gaac5399a034245e8adaa09f301bc4968c"><td class="mdescLeft">&#160;</td><td class="mdescRight">1 = A Master issued a GC  <a href="group__iic__v3__1.html#gaac5399a034245e8adaa09f301bc4968c">More...</a><br /></td></tr>
<tr class="separator:gaac5399a034245e8adaa09f301bc4968c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab0fe4841630cc66a6b93e5a5d2512fde"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#gab0fe4841630cc66a6b93e5a5d2512fde">XIIC_SR_ADDR_AS_SLAVE_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:gab0fe4841630cc66a6b93e5a5d2512fde"><td class="mdescLeft">&#160;</td><td class="mdescRight">1 = When addressed as slave  <a href="group__iic__v3__1.html#gab0fe4841630cc66a6b93e5a5d2512fde">More...</a><br /></td></tr>
<tr class="separator:gab0fe4841630cc66a6b93e5a5d2512fde"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga41bc9ddb46bd9eca389b60503e7a0589"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga41bc9ddb46bd9eca389b60503e7a0589">XIIC_SR_BUS_BUSY_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:ga41bc9ddb46bd9eca389b60503e7a0589"><td class="mdescLeft">&#160;</td><td class="mdescRight">1 = Bus is busy  <a href="group__iic__v3__1.html#ga41bc9ddb46bd9eca389b60503e7a0589">More...</a><br /></td></tr>
<tr class="separator:ga41bc9ddb46bd9eca389b60503e7a0589"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga98dda884f247690398dfd64b358c8769"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga98dda884f247690398dfd64b358c8769">XIIC_SR_MSTR_RDING_SLAVE_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga98dda884f247690398dfd64b358c8769"><td class="mdescLeft">&#160;</td><td class="mdescRight">1 = Dir: Master &lt;&ndash; slave  <a href="group__iic__v3__1.html#ga98dda884f247690398dfd64b358c8769">More...</a><br /></td></tr>
<tr class="separator:ga98dda884f247690398dfd64b358c8769"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9ccf53df4527f615d7b6b640a5e7a5e8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga9ccf53df4527f615d7b6b640a5e7a5e8">XIIC_SR_TX_FIFO_FULL_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:ga9ccf53df4527f615d7b6b640a5e7a5e8"><td class="mdescLeft">&#160;</td><td class="mdescRight">1 = Tx FIFO full  <a href="group__iic__v3__1.html#ga9ccf53df4527f615d7b6b640a5e7a5e8">More...</a><br /></td></tr>
<tr class="separator:ga9ccf53df4527f615d7b6b640a5e7a5e8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadccbbf3c41f7d44b6e1a85d72157ed08"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#gadccbbf3c41f7d44b6e1a85d72157ed08">XIIC_SR_RX_FIFO_FULL_MASK</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:gadccbbf3c41f7d44b6e1a85d72157ed08"><td class="mdescLeft">&#160;</td><td class="mdescRight">1 = Rx FIFO full  <a href="group__iic__v3__1.html#gadccbbf3c41f7d44b6e1a85d72157ed08">More...</a><br /></td></tr>
<tr class="separator:gadccbbf3c41f7d44b6e1a85d72157ed08"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaee53acd662dfc1cca568f88401620780"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#gaee53acd662dfc1cca568f88401620780">XIIC_SR_RX_FIFO_EMPTY_MASK</a>&#160;&#160;&#160;0x00000040</td></tr>
<tr class="memdesc:gaee53acd662dfc1cca568f88401620780"><td class="mdescLeft">&#160;</td><td class="mdescRight">1 = Rx FIFO empty  <a href="group__iic__v3__1.html#gaee53acd662dfc1cca568f88401620780">More...</a><br /></td></tr>
<tr class="separator:gaee53acd662dfc1cca568f88401620780"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3e6ab2b0daa0a08862d649fb769f87e9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga3e6ab2b0daa0a08862d649fb769f87e9">XIIC_SR_TX_FIFO_EMPTY_MASK</a>&#160;&#160;&#160;0x00000080</td></tr>
<tr class="memdesc:ga3e6ab2b0daa0a08862d649fb769f87e9"><td class="mdescLeft">&#160;</td><td class="mdescRight">1 = Tx FIFO empty  <a href="group__iic__v3__1.html#ga3e6ab2b0daa0a08862d649fb769f87e9">More...</a><br /></td></tr>
<tr class="separator:ga3e6ab2b0daa0a08862d649fb769f87e9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Data Tx Register (DTR) mask(s)</div></td></tr>
<tr class="memitem:ga958c3a8926423eed1b2c16aa56938257"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga958c3a8926423eed1b2c16aa56938257">XIIC_TX_DYN_START_MASK</a>&#160;&#160;&#160;0x00000100</td></tr>
<tr class="memdesc:ga958c3a8926423eed1b2c16aa56938257"><td class="mdescLeft">&#160;</td><td class="mdescRight">1 = Set dynamic start  <a href="group__iic__v3__1.html#ga958c3a8926423eed1b2c16aa56938257">More...</a><br /></td></tr>
<tr class="separator:ga958c3a8926423eed1b2c16aa56938257"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7efb5db8358e4ce8fa761d0227f52fba"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga7efb5db8358e4ce8fa761d0227f52fba">XIIC_TX_DYN_STOP_MASK</a>&#160;&#160;&#160;0x00000200</td></tr>
<tr class="memdesc:ga7efb5db8358e4ce8fa761d0227f52fba"><td class="mdescLeft">&#160;</td><td class="mdescRight">1 = Set dynamic stop  <a href="group__iic__v3__1.html#ga7efb5db8358e4ce8fa761d0227f52fba">More...</a><br /></td></tr>
<tr class="separator:ga7efb5db8358e4ce8fa761d0227f52fba"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9f43797e583841a89bfc81c9d2b8bd1b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga9f43797e583841a89bfc81c9d2b8bd1b">IIC_TX_FIFO_DEPTH</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:ga9f43797e583841a89bfc81c9d2b8bd1b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tx fifo capacity.  <a href="group__iic__v3__1.html#ga9f43797e583841a89bfc81c9d2b8bd1b">More...</a><br /></td></tr>
<tr class="separator:ga9f43797e583841a89bfc81c9d2b8bd1b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Data Rx Register (DRR) mask(s)</div></td></tr>
<tr class="memitem:ga23db93d1ef8c4651eba08f22fff2ee36"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga23db93d1ef8c4651eba08f22fff2ee36">IIC_RX_FIFO_DEPTH</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:ga23db93d1ef8c4651eba08f22fff2ee36"><td class="mdescLeft">&#160;</td><td class="mdescRight">Rx fifo capacity.  <a href="group__iic__v3__1.html#ga23db93d1ef8c4651eba08f22fff2ee36">More...</a><br /></td></tr>
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</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:ga7a848238d75ff57837afa5a58f11f326"><td class="memItemLeft" align="right" valign="top">unsigned&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga7a848238d75ff57837afa5a58f11f326">XIic_Recv</a> (UINTPTR BaseAddress, u8 Address, u8 *BufferPtr, unsigned ByteCount, u8 Option)</td></tr>
<tr class="memdesc:ga7a848238d75ff57837afa5a58f11f326"><td class="mdescLeft">&#160;</td><td class="mdescRight">Receive data as a master on the IIC bus.  <a href="group__iic__v3__1.html#ga7a848238d75ff57837afa5a58f11f326">More...</a><br /></td></tr>
<tr class="separator:ga7a848238d75ff57837afa5a58f11f326"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga907c577b53407fb0bfc98d0ca37ee221"><td class="memItemLeft" align="right" valign="top">unsigned&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga907c577b53407fb0bfc98d0ca37ee221">XIic_Send</a> (UINTPTR BaseAddress, u8 Address, u8 *BufferPtr, unsigned ByteCount, u8 Option)</td></tr>
<tr class="memdesc:ga907c577b53407fb0bfc98d0ca37ee221"><td class="mdescLeft">&#160;</td><td class="mdescRight">Send data as a master on the IIC bus.  <a href="group__iic__v3__1.html#ga907c577b53407fb0bfc98d0ca37ee221">More...</a><br /></td></tr>
<tr class="separator:ga907c577b53407fb0bfc98d0ca37ee221"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9979fbd483e1c8c495c9eb2bfd7ad6e9"><td class="memItemLeft" align="right" valign="top">unsigned&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga9979fbd483e1c8c495c9eb2bfd7ad6e9">XIic_DynRecv</a> (UINTPTR BaseAddress, u8 Address, u8 *BufferPtr, u8 ByteCount)</td></tr>
<tr class="memdesc:ga9979fbd483e1c8c495c9eb2bfd7ad6e9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Receive data as a master on the IIC bus.  <a href="group__iic__v3__1.html#ga9979fbd483e1c8c495c9eb2bfd7ad6e9">More...</a><br /></td></tr>
<tr class="separator:ga9979fbd483e1c8c495c9eb2bfd7ad6e9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadeaf11cda2466ae1c6036a3de0f52874"><td class="memItemLeft" align="right" valign="top">unsigned&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#gadeaf11cda2466ae1c6036a3de0f52874">XIic_DynSend</a> (UINTPTR BaseAddress, u16 Address, u8 *BufferPtr, u8 ByteCount, u8 Option)</td></tr>
<tr class="memdesc:gadeaf11cda2466ae1c6036a3de0f52874"><td class="mdescLeft">&#160;</td><td class="mdescRight">Send data as a master on the IIC bus.  <a href="group__iic__v3__1.html#gadeaf11cda2466ae1c6036a3de0f52874">More...</a><br /></td></tr>
<tr class="separator:gadeaf11cda2466ae1c6036a3de0f52874"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga90f3806cf4817250596f6f68f2c066a3"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga90f3806cf4817250596f6f68f2c066a3">XIic_WaitBusFree</a> (UINTPTR BaseAddress)</td></tr>
<tr class="memdesc:ga90f3806cf4817250596f6f68f2c066a3"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will wait until the I2C bus is free or timeout.  <a href="group__iic__v3__1.html#ga90f3806cf4817250596f6f68f2c066a3">More...</a><br /></td></tr>
<tr class="separator:ga90f3806cf4817250596f6f68f2c066a3"><td class="memSeparator" colspan="2">&#160;</td></tr>
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